1. Test-mode-only scan attack and countermeasure for contemporary scan architectures - ITC 2014
2. AES design space exploration new line for scan attack resiliency - VLSI-SoC 2014
3. Test-mode-only scan attack using the boundary scan chain - ETS 2014
4. New scan attacks against state-of-the-art countermeasures and DFT - HOST 2014
5. New scan-based attack using only the test mode - VLSI-SoC 2013
6. Improved differential fault analysis of CLEFIA - FATC 2013
7. Scan attack in presence of mode-reset countermeasure - IOLTS 2013
8. Differential fault analysis of AES: towards reaching its limits - JCE 2013
9. A fault analysis perspective for testing of secured soc cores - IEEE Design & Test 2013
10. Differential fault analysis of Twofish - Inscrypt 2012
11.Protecting last four rounds of CLEFIA is not enough against differential fault analysis - IACR 2012
12. A differential fault analysis on AES key schedule using single fault - FDTC 2011
13. Multi-level attacks: An emerging security concern for cryptographic hardware - DAT 2011
14. Differential fault analysis of AES-128 key schedule using a single multi-byte fault - CARDIS 2011
15. An improved differential fault analysis on AES-256 - AFRICACRYPT 2011
16. Differential fault analysis of the advanced encryption standard using a single fault - IACR 2011
17. Acceleration of Differential Fault Analysis of the Advanced Encryption Standard Using Single Fault - IACR 2010
18. Differential fault analysis of AES using a single multiple-byte fault - IACR 2010














 

1. Guest Editorial SPACE 2017 Special Issue in the Journal of Hardware and Systems Security - HaSS 2017
2. Scan Design: Basics, Advancements, and Vulnerabilities - HST 2017
3. A compact implementation of Salsa20 and its power analysis vulnerabilities - TODAES 2017
4. A comparative security analysis of current and emerging technologies - IEEE Micro 2016
5. Microfluidic encryption of on-chip biochemical assays - IEEE BioCAS 2016
6. Supply-Chain Security of Digital Microfluidic Biochips - IEEE Computer Society 2016
7. Power-side-channel analysis of carbon nanotube FET based design - IEEE IOLTS 2016
8. Thwarting timing attacks on NEMS relay based designs - IEEE VTS 2016
9. Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers  - IEEE TETC 2016
10. Fault Attacks on AES and Their Countermeasures - IEEE Micro 2016
11. Novel test-mode-only scan attack and countermeasure for compression-based scan architectures - IEEE Tcad 2015
12. TMO: A new class of attack on cipher misusing test infrastructure  - IEEE VTS 2015
13. A secure design-for-test infrastructure for lifetime security of SoCs  - IEEE ISCAS 2015
14. Power analysis attacks on ARX: an application to Salsa20  - IEEE IOLTS 2015
15. Can assay outcomes of digital microfluidic biochips be manipulated? - IEEE ICCD 2015
16. Timing attack on NEMS relay based design of AES - IEEE VLSI-SOC 2015
17. Security analysis of logic encryption against the most effective side-channel attack: DPA  - IEEE DFTS 2015
18. Scan attack on elliptic curve cryptosystem  - IEEE DFTS 2015
19. Security implications of cyber physical digital microfluidic biochips - IEEE ICCD 2015
20. Security assessment of cyber physical digital microfluidic biochips  - IEEE/ACM TCBB 2015

1. Security Analysis of Scan Obfuscation Techniques - IEEE TIFS 2023
2. On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective - ACM ETCS 2023
3. Evaluating Security of New Locking SIB-based Architectures - ETS 2022
4. Security Analysis of State-of-the-art Scan Obfuscation Technique - IEEE ICCD 2021
5. Co-relation scan attack analysis (COSAA) on AES: A comprehensive approach - ELSEVIER 2021
6. Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks - ETS 2021