Secure Design for Testability
Post-manufacturing, a chip has to be tested for possible manufacture related faults. Scan-based DfT is the most widely used test infrastructure in an effort to enhance access, and thus, testability. However, for security-critical chips, the same test infrastructure can be misused to leak secret information in the form of test responses of the chip while testing. Recently, we have identified a list of vulnerabilities in the scan obfuscation based defense mechanism. We have shown that most of these defense mechanisms are vulnerable to differential scan attacks. We have shown a new cost-effective defense mechanism by leveraging the S-box hamming weight model.